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general description the max15022 is a dual-output, pulse-width-modulated (pwm), step-down dc-dc regulator with dual ldo con- trollers. the device operates from 2.5v to 5.5v and each output can be adjusted from 0.6v to the input supply (v avin ). the max15022 delivers up to 4a (regu- lator 1) and 2a (regulator 2) of output current with two ldo controllers that can be used to drive two external pnp transistors to provide two additional outputs. this device offers the ability to adjust the switching frequen- cy from 500khz to 4mhz and provides the capability of optimizing the design in terms of size and performance. the max15022 utilizes a voltage-mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. the dual switching regula- tors operate 180 out-of-phase, thereby reducing the rms input ripple current and thus the size of the input bypass capacitor significantly. the max15022 offers the ability to track (coincident or ratiometric) or sequence during power-up and power- down operation. when sequencing, it powers up glitch- free into a prebiased output. additional features include an internal undervoltage lockout with hysteresis and a digital soft-start/soft-stop for glitch-free power-up and power-down. protection features include lossless cycle-by-cycle current limit, hiccup-mode output short-circuit protection, and ther- mal shutdown. the max15022 is available in a space-saving, 5mm x 5mm, 28-pin tqfn-ep package and is specified for operation from -40c to +125c temperature range. applications rfid reader cards power-over-ethernet (poe) ip phones automotive multimedia multivoltage supplies networking/telecom features 2.5v to 5.5v input-voltage range dual-output synchronous buck regulators integrated switches for 4a and 2a output currents 180 out-of-phase operation output voltage adjustable from 0.6v to v avin two ldo controllers lossless, cycle-by-cycle current sensing external compensation for maximum flexibility digital soft-start and soft-stop for tracking applications digital soft-start into a prebiased load for sequencing applications sequencing or coincident/ratiometric tracking programmable switching frequency from 500khz to 4mhz thermal shutdown and hiccup-mode short- circuit protection 30? shutdown current 100% maximum duty cycle space-saving (5mm x 5mm) 28-pin tqfn package max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers ________________________________________________________________ maxim integrated products 1 max15022 thin qfn (5mm x 5mm) top view 26 27 25 24 10 9 11 pgnd1 pvin1 pvin1 lx1 pgnd1 12 sel en4 lx2 pgnd2 fb4 dvdd2 en3 1 + 2 en2 4 *ep *ep = exposed pad. 567 20 21 19 17 16 15 sgnd avin comp1 fb1 en1 dvdd1 lx1 pvin2 3 18 28 8 rt pgnd1 fb2 23 13 b3 comp2 22 14 fb3 b4 pin configuration ordering information 19-4107; rev 1; 7/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package MAX15022ATI+ -40c to +125c 28 tqfn-ep* MAX15022ATI/v+ -40c to +125c 28 tqfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. /v denotes an automotive qualified part.
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v avin = v pvin_ = v dvdd_ = 3.3v, v pgnd_ = v sgnd = 0v, r t = 25k ? , and t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25?.) (note 3) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: lx has internal diodes to pgnd_ and pvin_. applications that forward bias these diodes should take care not to exceed the ic? package power dissipation limits. avin, pvin_, b_, dvdd_, en_, fb_, rt, sel to sgnd .........................................................-0.3v to +6v comp_ to sgnd .....................................-0.3v to (v avin + 0.3v) pgnd_ to sgnd ...................................................-0.3v to +0.3v lx current (note 1) regulator 1...............................................................................6a regulator 2...............................................................................3a current into any pin other than pvin_, lx_ and pgnd_.............................................................?0ma continuous power dissipation (t a = +70?) tqfn (derate 34.5mw/? above +70?) ................2758.6mw operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units system specifications input-voltage range v avin = v pvin1 = v pvin2 = v dvdd1 = v dvdd2 2.5 5.5 v undervoltage lockout threshold avin rising 2.1 2.2 2.3 v undervoltage lockout hysteresis 0.12 v operating supply current v en_ = 1.3v, v fb_ = 0.8v 3.5 6 ma shutdown supply current v en_ = 0v 30 65 ? pwm digital soft-start/soft-stop soft-start/soft-stop duration 4096 clock cycles reference voltage steps 64 steps pwm error amplifiers fb1, fb2 input bias current -1 +1 ? fb1, fb2 voltage set-point 0.593 0.599 0.605 v comp1, comp2 voltage range i comp _ = -250? to +250? 0.3 v avin - 0.5 v error-amplifier open-loop gain 80 db error-amplifier unity-gain bandwidth 12 mhz note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . package thermal characteristics (note 2) tqfn junction-to-ambient thermal resistance ( ja )...............29?/w junction-to-case thermal resistance ( jc )......................2?/w
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v avin = v pvin_ = v dvdd_ = 3.3v, v pgnd_ = v sgnd = 0v, r t = 25k ? , and t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 3) parameter symbol conditions min typ max units ldo controllers fb3, fb4 input bias current -250 +250 na fb3, fb4 voltage set-point 5ma sink current, v b_ = 0.5v to 5.5v 0.585 0.600 0.615 v fb3, fb4 to b3, b4 transconductance 2.5ma to 10ma sink current, v b_ = 0.5v to 5.5v 0.56 1.20 2.30 s b3, b4 driver sink current v fb3, v fb4 = 0v, v b_ = 0.5v to 5.5v 20 ma ldo soft-start duration 512 clock cycles ldo reference voltage steps 64 steps power mosfets regulator 1 p-channel mosfet r dson v dvdd1 = 5v 50 90 m ? regulator 1 n-channel mosfet r dson v dvdd1 = 5v 30 50 m ? regulator 1 gate charge v dvdd1 = 5v 8 nc maximum lx1 rms current 4a regulator 2 p-channel mosfet r dson v dvdd2 = 5v 100 180 m ? regulator 2 n-channel mosfet r dson v dvdd2 = 5v 60 100 m ? regulator 2 gate charge v dvdd2 = 5v 4 nc maximum lx2 rms current 2a pwm current limit and hiccup mode v pvin = v avin = 3.3v 4.5 4.9 5.3 regulator 1 peak current limit v pvin = v avin = 2.5v 3.40 3.65 3.95 a v pvin = v avin = 3.3v 4.0 5.0 5.65 regulator 1 valley current limit v pvin = v avin = 2.5v 3.0 3.7 4.25 a v pvin = v avin = 3.3v 2.25 2.45 2.65 regulator 2 peak current limit v pvin = v avin = 2.5v 1.70 1.85 1.98 a v pvin = v avin = 3.3v 2.0 2.5 2.83 regulator 2 valley current limit v pvin = v avin = 2.5v 1.5 1.85 2.13 a number of cumulative current- limit events to hiccup n cl 4 clock cycles number of consecutive noncurrent limit cycles to clear n cl n clr 3 clock cycles hiccup timeout n ht 8192 clock cycles
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers 4 _______________________________________________________________________________________ electrical characteristics (continued) (v avin = v pvin_ = v dvdd_ = 3.3v, v pgnd_ = v sgnd = 0v, r t = 25k ? , and t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 3) parameter symbol conditions min typ max units enable/sel en_ threshold v en_ rising 1.207 1.225 1.243 v en_ hysteresis 0.12 v en_ input current -2.5 +2.5 a sel high threshold 0.85 x v avin v sel low threshold 0.2 x v avin v sel input bias current present only during startup -100 +100 a oscillator switching frequency range f sw f sw = 4mhz x [v rt (v)/1.067(v)] (note 4) 4000 khz f sw 1500khz -6 +6 oscillator accuracy f sw > 1500khz -10 +10 % phase shift between regulators 180 degrees rt current 0 < v rt < 1.067v 31.30 32.00 32.58 a rt voltage range v rt 0.130 1.067 v minimum controllable on-time 60 ns minimum controllable off-time 60 ns pwm ramp amplitude v avin /4 v pwm ramp valley 0.3 v thermal shutdown thermal shutdown temperature temperature rising +160 c thermal shutdown hysteresis 15 c note 3: specifications are 100% production tested at t a = +25c and t a = +125c. maximum and minimum specifications over temperature are guaranteed by design. note 4: when operating with v avin = 2.5v, the maximum operating frequency should be derated to 3mhz.
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers _______________________________________________________________________________________ 5 typical operating characteristics (v avin = v dvdd1 = v dvdd2 = v pvin1 = v pvin2 = 5v, v out1 = 3.3v, v out2 = 1.5v, v pgnd_ = 0v, r t = 16.5k ? . t a = +25c, unless otherwise noted.) channel 1 efficiency vs. load current max15022 toc01 load current (ma) efficiency (%) 1000 10 20 30 40 50 60 70 80 90 100 0 100 5000 v pvin1 = 3.3v v pvin1 = 5v v out1 = 1.8v f sw = 2mhz en2 = 0v channel 1 efficiency vs. load current max15022 toc02 load current (ma) efficiency (%) 1000 10 20 30 40 50 60 70 80 90 100 0 100 5000 v pvin1 = 5v f sw = 2mhz en2 = 0v v out1 = 3.3v v out1 = 1.8v v out1 = 1.0v channel 2 efficiency vs. load current max15022 toc03 load current (ma) efficiency (%) 1000 10 20 30 40 50 60 70 80 90 100 0 100 3000 p vin2 = 5v p vin2 = 3.3v v out2 = 1.5v f sw = 2mhz en1 = 0v channel 2 efficiency vs. load current max15022 toc04 load current (ma) efficiency (%) 1000 10 20 30 40 50 60 70 80 90 100 0 100 3000 v out2 = 1.0v v out2 = 1.5v v out2 = 2.5v v pvin2 = 5v f sw = 2mhz en1 = 0v channel 1 load regulation max15022 toc05 load current (a) v out1 (v) 3.302 3.304 3.306 3.308 3.310 3.312 3.314 3.316 3.318 3.320 3.300 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 4.0 v pvin1 = 5v f sw = 2mhz channel 2 load regulation max15022 toc06 load current (a) v out2 (v) 1.25 1.00 0.75 0.50 0.25 1.5025 1.5030 1.5035 1.5040 1.5045 1.5050 1.5055 1.5060 1.5065 1.5070 1.5020 0 1.50 1.75 2.00 f sw = 2mhz v pvin2 = 5v v pvin2 = 3.3v switching frequency vs. rt resistance max15022 toc07 rt resistance (k ? ) switching frequency (mhz) 35 30 20 25 10 15 5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0 switching frequency vs. temperature max15022 toc08 temperature ( c) change in switching frequency (%) 110 95 65 80 -10 5 20 35 50 -25 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 -40 125 f sw = 2mhz
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers 6 _______________________________________________________________________________________ quiescent current vs. temperature max15022 toc09 temperature ( c) quiescent current (ma) 110 95 65 80 -10 5 20 35 50 -25 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 2.50 -40 125 no switching switching current vs. temperature max15022 toc10 temperature ( c) switching current (ma) 110 95 65 80 -10 5 20 35 50 -25 14 13 15 16 17 18 19 20 21 22 23 24 25 26 27 12 -40 125 regulator 1 enabled v out1 = 3.3v regulator 2 enabled v out2 = 1.5v normalized undervoltage lockout threshold vs. temperature max15022 toc11 temperature ( c) normalized uvlo threshold 110 95 65 80 -10 5 20 35 50 -25 0.975 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 1.030 0.970 -40 125 v uvlo (nom) = 2.2v coincident tracking soft-start max15022 toc13 v avin 5v/div v out1 1v/div v out2 1v/div 0v 0v 1ms/div coincident tracking soft-stop max15022 toc14 v avin 5v/div 1v/div 0v 0v 400 s/div v out2 en1 v out1 typical operating characteristics (continued) (v avin = v dvdd1 = v dvdd2 = v pvin1 = v pvin2 = 5v, v out1 = 3.3v, v out2 = 1.5v, v pgnd_ = 0v, r t = 16.5k ? . t a = +25c, unless otherwise noted.) en_ threshold vs. temperature max15022 toc12 temperature ( c) en_ threshold (v) 110 95 -25 -10 5 35 50 65 20 80 -40 125 1.215 1.220 1.225 1.230 1.235 1.240 1.245 1.250 1.255 1.260 1.210
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers _______________________________________________________________________________________ 7 channel 2 load step response max15022 toc17 v pvin2 5v/div v out2 1.5v, ac-coupled 100mv/div i out2 1a/div 0v 0a 20 s/div en1 = 0v 180 out-of-phase operation max15022 toc19 pvin1 = pvin2 5v/div v lx1 5v/div v lx2 5v/div 0v 0v 0v 200ns/div iout1 = 3a iout2 = 1.5a channel 3 and channel 4 output- voltage deviation vs. load current max15022 toc20 load current (ma) output-voltage deviation (mv) 450 400 350 300 250 200 150 100 50 2 4 6 8 10 12 14 0 0 500 channel 3, v in = 3.3v, v out3 = 2.5v njt403op pnp channel 4, v in = 2.5v, v out4 = 1.5v njt403op pnp channel 2 load step response max15022 toc18 v pvin2 5v/div v out2 1.5v, ac-coupled 100mv/div i out2 1a/div 0v 0a 20 s/div en1 = 0v typical operating characteristics (continued) (v avin = v dvdd1 = v dvdd2 = v pvin1 = v pvin2 = 5v, v out1 = 3.3v, v out2 = 1.5v, v pgnd_ = 0v, r t = 16.5k ? . t a = +25c, unless otherwise noted.) channel 1 load step response max15022 toc15 v pvin1 5v/div v out1 3.3v, ac-coupled 100mv/div i out1 2a/div 0v 0a 20 s/div en2 = 0v channel 1 load step response max15022 toc16 v pvin1 5v/div v out1 3.3v, ac-coupled 100mv/div i out1 2a/div 0v 0a 20 s/div en2 = 0v
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers 8 _______________________________________________________________________________________ pin description pin name function 1 sel track/sequence select input. connect sel to sgnd to configure the device as a sequencer. connect sel to avin for tracking with output 1 as the master. leave sel unconnected for tracking with output 2 as the master. use the output with the higher voltage as the master and the output with the lower voltage as the slave. 2, 7, 8 pgnd1 power ground connection for regulator 1. connect the negative terminals of the input and output filter capacitors to pgnd1. connect pgnd1 externally to sgnd at a single point, typically at the negative terminal of the input bypass capacitor. 3, 6 lx1 inductor connection for regulator 1. lx1 is the drain connection of the internal high-side p-channel mosfet and the drain connection of the internal synchronous n-channel mosfet for regulator 1. 4, 5 pvin1 input supply voltage for regulator 1. connect pvin1 to an external voltage source from 2.5v to 5.5v. bypass pvin1 to pgnd1 with a 1f (min) ceramic capacitor. 9 dvdd1 switch driver supply for regulator 1. connect externally to pvin1. 10 en1 enable input for regulator 1. when configured as a sequencer, en1 must exceed 1.225v (typ) for the pwm controller to begin regulating output 1. when configured as a tracker, connect en1 to the center tap of a resistive divider from the regulator 2 output. 11 fb1 feedback regulation point for regulator 1. connect fb1 to the center tap of a resistive divider from the regulator 1 output to sgnd to set the output voltage. the fb1 voltage regulates to 0.6v (typ). 12 comp1 error-amplifier output for regulator 1. connect comp1 to the compensation feedback network. channel 3 output voltage vs. input voltage max15022 toc21 supply voltage (v) output voltage (v) 4.98 4.46 3.94 3.42 2.455 2.460 2.465 2.470 2.475 2.480 2.485 2.490 2.495 2.500 2.450 2.90 5.50 i out3 = 500ma i out3 = 10ma v out3 = 2.5v channel 4 output voltage vs. input voltage max15022 toc22 supply voltage (v) output voltage (v) 4.98 4.46 3.94 3.42 1.175 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.170 2.90 5.50 i out4 = 10ma i out4 = 500ma v out4 = 1.5v ldo power-supply rejection ratio max15022 toc23 frequency (hz) psrr (db) 100 -70 -60 -50 -40 -30 -20 -10 0 -80 10 1000 v in = 3.3v, v out3 = 2.5v, i out3 = 10ma, 100mv p-p signal applied to v in typical operating characteristics (continued) (v avin = v dvdd1 = v dvdd2 = v pvin1 = v pvin2 = 5v, v out1 = 3.3v, v out2 = 1.5v, v pgnd_ = 0v, r t = 16.5k ? . t a = +25c, unless otherwise noted.)
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers _______________________________________________________________________________________ 9 pin description (continued) pin name function 13 b3 transconductance amplifier open-drain output for ldo controller 3. connect b3 to the base of an external pnp transistor to regulate output 3. 14 fb3 feedback regulation point for ldo controller 3. connect to the center tap of a resistive divider from the output 3 to sgnd to set the output voltage. the fb3 voltage regulates to 0.6v (typ). 15 en3 ldo enable input for ldo controller 3. en3 must exceed 1.225v (typ) for the ldo controller to begin regulating output 3. 16 dvdd2 switch driver supply for regulator 2. connect externally to pvin2. 17 pgnd2 power ground connection for regulator 2. connect the negative terminals of the input and output filter capacitors to pgnd2. connect pgnd2 externally to sgnd at a single point, typically at the negative terminal of the input bypass capacitor. 18 lx2 inductor connection for regulator 2. lx2 is the drain connection of the internal high-side p-channel mosfet and the drain connection of the internal synchronous n-channel mosfet for regulator 2. 19 pvin2 input supply voltage for regulator 2. connect to an external voltage source from 2.5v to 5.5v. bypass pvin2 to pgnd2 with a 1f (min) ceramic capacitor. 20 en4 ldo enable input for ldo controller 4. en4 must exceed 1.225v (typ) for the ldo controller to begin regulating output 4. 21 fb4 feedback regulation point for ldo controller 4. connect to the center tap of a resistive divider from output 4 to sgnd to set the output voltage. the fb4 voltage regulates to 0.6v (typ). 22 b4 transconductance amplifier open-drain output for ldo controller 4. connect b4 to the base of an external pnp transistor to regulate output 4. 23 comp2 error-amplifier output for regulator 2. connect comp2 to the compensation feedback network. 24 fb2 feedback regulation point for regulator 2. connect to the center tap of a resistive divider from the regulator 2 output to sgnd to set the output voltage. the fb2 voltage regulates to 0.6v (typ). 25 en2 enable input for regulator 2. when configured as a sequencer, en2 must exceed 1.225v (typ) for the pwm controller to begin regulating output 1. when configured as a tracker, connect en2 to the center tap of a resistive divider from the regulator 1 output. 26 sgnd signal ground. connect sgnd to pgnd_ at a single point, typically near the negative terminal of the input bypass capacitor. 27 avin input voltage. bypass avin to sgnd with a 100nf (min) ceramic capacitor. 28 rt oscillator timing resistor connection. connect a 4.2k ? to 33k ? resistor from rt to sgnd to program the switching frequency from 500khz to 4mhz. ep exposed paddle. connect ep to a large copper plane at sgnd potential to improve thermal dissipation. do not use as the main sgnd connection.
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers 10 ______________________________________________________________________________________ functional diagrams max15022 res avin sel sgnd pwm controller 1 clk1 rt comp1 fb1 v ref 1.225v 1.1v seq1 on1 on2 seq1 shdn seq2 on1 seq1 seq1 clk1 clk2 level shift seq2 ovl1 ilim1 ovl1 pgnd1 lx1 ovl2 shdn clk1 clk2 down1 e/a cpwm v r1 en1 0.6v ref v ref ramp en osc thermal shdn ovl config en config sel decode overload management digital soft-start and soft-stop 1.225v 1.1v d r break- before- make q avin high-side current sense low-side current sense clk dvdd1 en1 pvin1
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers ______________________________________________________________________________________ 11 functional diagrams (continued) max15022 res pwm controller 2 dual ldo controllers clk2 seq2 on2 en2 comp2 fb2 v ref 1.225v 1.1v seq1 on1 on2 seq1 seq2 seq1 clk2 level shift seq2 ovl2 ilim2 v ref ovl1 pgnd2 lx2 ovl2 shdn clk1 clk2 down2 e/a cpwm v r2 en2 v ref ramp ovl config clk2 digital soft-start en config overload management digital soft-start and soft-stop en4 en3 1.25v 1.125v shdn d r break- before- make q avin high-side current sense low-side current sense clk dvdd2 b4 pvin2 fb4 v ref shdn clk1 digital soft-start 1.225v 1.1v b3 fb3
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers 12 ______________________________________________________________________________________ detailed description the max15022 incorporates dual-output, pwm, step- down, dc-dc regulators and dual ldo controllers with tracking and sequencing options. the device operates over the input-voltage range of 2.5v to 5.5v. each pwm regulator provides an adjustable output down to 0.6v and delivers up to 4a (regulator 1) and 2a (regulator 2) of load current. the high switching frequency (up to 4mhz) and integrated power switches optimize the max15022 for high-performance and small-size power management solutions. each of the max15022 pwm regulator sections utilizes a voltage-mode control scheme for good noise immuni- ty and offers external compensation allowing for maxi- mum flexibility with a wide selection of inductor values and capacitor types. the device operates at a fixed switching frequency that is programmable from 500khz to 4mhz with a single resistor. operating the regulators with 180 out-of-phase clocking, and at frequencies up to 4mhz, significantly reduces the rms input ripple current. the resulting peak input current reduction (and increase in the ripple frequency) significantly reduces the required amount of input bypass capacitance. the max15022 provides coincident tracking, ratiomet- ric tracking, or sequencing to allow tailoring of power- up/power-down sequence depending on the system requirements. when sequencing, it powers up glitch- free into a prebiased output. the max15022 features two ldo controllers for external pnp pass transistors to provide two additional outputs. the max15022 includes internal undervoltage lockout with hysteresis, digital soft-start/soft-stop for glitch-free power-up and power-down. protection features include lossless, cycle-by-cycle current limit, hiccup-mode out- put short-circuit protection, and thermal shutdown. undervoltage lockout (uvlo) the supply voltage (v avin ) must exceed the default uvlo threshold before any operation starts. the uvlo circuitry keeps the mosfet drivers, oscillator, and all the internal circuitry shut down to reduce current con- sumption. the uvlo rising threshold is 2.2v (typ) with a 120mv (typ) hysteresis. digital soft-start/soft-stop the max15022 soft-start feature allows the load volt- age to ramp up in a controlled manner, eliminating out- put-voltage overshoot. soft-start begins after v avin exceeds the undervoltage lockout threshold and the enable input is above 1.225v (typ). the soft-start cir- cuitry ramps up the reference voltage, controlling the rate of rise of the output voltage, and reducing input surge currents during startup. the soft-start duration is 4096 clock cycles. the output voltage is incremented through 64 equal steps. the output reaches regulation when soft-start is completed, regardless of the output capacitance and load. for tracking applications, soft-stop commences when the enable input falls below 1.1v (typ). the soft-stop circuitry ramps down the reference voltage controlling the output- voltage rate of fall. the output voltage is decremented through 64 equal steps in 4096 clock cycles. oscillator use an external resistor at rt to program the max15022 switching frequency from 500khz to 4mhz. calculate the appropriate resistor value at rt for the desired output switching frequency (f sw ): tracking/sequencing the max15022 features coincident/ratiometric tracking and sequencing (see figure 1). connect sel to ground to configure the device as a sequencer. connect sel to avin for tracking with output 1 as the master. leave sel unconnected for tracking with output 2 as the master. assign the output with the higher voltage as the master. rk a t [] . [] ?= f [khz] 1 [v] 4[mhz] sw 067 32 v out1 soft-start soft-start soft-start soft-stop a) coincident tracking outputs b) ratiometric tracking outputs c) sequenced outputs soft-stop soft-stop v out2 v out1 v out2 v out1 v out2 figure 1. graphical representation of coincident tracking, ratiometric tracking, and sequencing
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers ______________________________________________________________________________________ 13 coincident/ratiometric tracking the enable inputs in conjunction with digital soft-start and soft-stop provide coincident/ratiometric tracking. track an output voltage by connecting a resistive divider from the output being tracked to its enable input. for example, for v out2 to coincidentally track v out1 , connect the same resistive divider used for fb2, from v out1 to en2 to sgnd (see figure 2). track ratiometrically by connecting en_ to sgnd. this synchonizes the soft-start and soft-stop of all the regu- lator references, and hence their respective output volt- ages will track ratiometrically (see figure 2). when the max15022 regulators are configured as volt- age trackers, output short-circuit fault conditions at either master or slave output are handled carefullynei- ther the master nor slave output will remain energized when the other output is shorted to ground. when the slave is shorted and enters into hiccup mode, the mas- ter will soft-stop. when the master is shorted and the part enters into hiccup mode, the slave will ratiometrical- ly soft-stop. coming out of hiccup mode, both outputs will soft-start coincidently or ratiometrically depending on their initial configuration. during the thermal shut- down or power-off when the input falls below its uvlo, the output voltages track down depending on the respective output capacitance and load. see figure 1 for a graphical representation of coinci- dent/ratiometric tracking. sequencing when sequencing, the voltage at the enable inputs must exceed 1.225v (typ) for each pwm controller to start (see figure 1c). v pvin1 en2 en1 sel avin output 1 is the master and output 2 is the slave. ratiometric tracking a) b) c) coincident tracking coincident tracking sel avin output 1 is the master and output 2 is the slave. v pvin1 r a r b r a r b en1 v out1 en2 v out2 fb2 sel unconnected output 2 is the master and output 1 is the slave. v pvin2 r c r d r c r d en2 v out2 en1 v out1 fb1 v pvin2 en1 en2 sel unconnected output 2 is the master and output 1 is the slave. figure 2. ratiometric tracking and coincident tracking configurations
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers 14 ______________________________________________________________________________________ error amplifier the output of the internal voltage-mode error amplifier (comp_) is provided for frequency compensation (see the compensation design guidelines section). fb_ is the inverting input of the error amplifier. the error amplifier has an 80db open-loop gain and a 12mhz gain bandwidth (gbw) product. output short-circuit protection (hiccup mode) the max15022 features lossless, high-side peak cur- rent limit and low-side, valley current limit. at short duty cycles, both limits are active. at high duty cycles, only the high-side peak current limit is active. either limit causes the hiccup mode counter (n cl ) to increment. for duty cycles less than 50%, the low-side valley cur- rent limit is active. once the high-side mosfet turns off, the voltage across the low-side mosfet is monitored. if this voltage does not exceed the current-limit threshold at the end of the cycle, the high-side mosfet turns on normally at the start of the next cycle. if the voltage exceeds the current-limit threshold just before the beginning of a new pwm cycle, the controller skips that cycle. during severe overload or short-circuit condi- tions, the switching frequency of the device appears to decrease because the on-time of the low-side mosfet extends beyond a clock cycle. if the current-limit threshold is exceeded for more than four cumulative clock cycles (n cl ), the device shuts down for 8192 clock cycles (hiccup timeout) and then restarts with a soft-start sequence. if three consecutive cycles pass without a current-limit event, the count of n cl is cleared (see figure 3). hiccup mode protects the device against a continuous output short circuit. the internal current limit is constant from 5.5v down to 3v and decreases linearly by 50% from 3v to 2v. see the electrical characteristics table. thermal-overload protection the max15022 features an integrated thermal-overload protection with temperature hysteresis. thermal-over- load protection limits the die temperature of the device and protects it in the event of an extended thermal fault condition. when the die temperature exceeds +160c, an internal thermal sensor shuts down the device, turn- ing off the internal power mosfets and allowing the die to cool. after the die temperature falls by +15c (typ), the device restarts with a soft-start sequence. startup into a prebiased output (sequencing mode) in sequencing mode, the regulators start with minimal glitch into a prebiased output and soft-stop is disabled. during soft-start, both switches are kept off until the pwm comparator commands its first pwm pulse. until then, the converters do not sink current from the out- puts. the first pwm pulse occurs when the ramping ref- erence voltage increases above the fb_ voltage. ldo controllers the max15022 provides two additional ldo controllers to drive external pnp pass transistors. connect the emit- ter of each pnp pass transistor to either the input supply or one of the controller 1 or 2 outputs. each ldo con- troller features an independent enable input and digital soft-start. connect fb3 and fb4 to the center tap of a resistive divider from the output of the desired ldo con- troller to sgnd to set the output voltage. pwm controllers design procedure setting the switching frequency connect a 4.2k ? to 33k ? resistor from rt to sgnd to program the switching frequency (f sw ) from 500khz to 4mhz. calculate the required resistor value r t to set the switching frequency with the following equation: higher frequencies allow designs with lower inductor values and less output capacitance. at higher switch- ing frequencies core losses, gate-charge currents, and switching losses increase. when operating from v avin < 3v, the f sw frequency should be derated to 3mhz (maximum). r f [khz] 1 [v] 32 4[mhz] t sw [] . [] k a ?= 067 current limit count of 4 n cl in clr initiate hiccup timeout n ht count of 3 n clr in clr figure 3. hiccup-mode block diagram
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers ______________________________________________________________________________________ 15 effective input-voltage range although the max15022s regulators can operate from input supplies ranging from 2.5v to 5.5v, the input-volt- age range can be effectively limited by the max15022s duty-cycle limitations for a given output voltage (v out_ ). the maximum input voltage (v pvin_max ) can be effectively limited by the control- lable minimum on-time (t on(min) ): where t on(min) is 0.06s (typ). the minimum input voltage (v pvin_min ) can be effec- tively limited by the maximum controllable duty cycle and is calculated using the following equation: where v out_ is the regulator output voltage and t off(min) is the 0.06s (typ) controllable off-time. inductor selection three key inductor parameters must be specified for operation with the max15022: inductance value (l), peak inductor current (i peak ), and inductor saturation current (i sat ). the minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current ( ? i p-p ). higher ? i p-p allows for a lower inductor value. a lower inductance minimizes size and cost and improves large-signal and transient response. however, efficiency is reduced due to higher peak cur- rents and higher peak-to-peak output-voltage ripple for the same output capacitor. a higher inductance increases efficiency by reducing the ripple current; however, resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current lev- els especially when the inductance is increased without also allowing for larger inductor dimensions. choose the inductors peak-to-peak current, ? i p-p, in the range of 20% to 50% of the full load current; as a rule of thumb 30% is typical. calculate the inductance, l, using the following equation: where v pvin_ is the input supply voltage, v out_ is the regulator output voltage, and f sw is the switching fre- quency. use typical values for v pvin_ and v out_ so that efficiency is optimum for typical conditions. the switching frequency (f sw ) is programmable between 500khz and 4mhz (see the oscillator section). the peak-to-peak inductor current ( ? i p-p ), which reflects the peak-to-peak output ripple, is largest at the maximum input voltage. see the output-capacitor selection section to verify that the worst-case output current ripple is acceptable. select an inductor with a saturation current, i sat , high- er than the maximum peak current to avoid runaway current during continuous output short-circuit condi- tions. also, confirm that the inductors thermal perfor- mances and projected temperature rise above ambient does not exceed its thermal capacity. many inductor manufacturers provide bias/load current versus tem- perature rise performance curves (or similar) to obtain this information. input-capacitor selection the discontinuous input current of the buck converter causes large input ripple currents and therefore the input capacitor must be carefully chosen to withstand the input ripple current and keep the input-voltage rip- ple within design requirements. the input-voltage ripple is comprised of ? v q (caused by the capacitor discharge) and ? v esr (caused by the esr of the input capacitor). the total voltage ripple is the sum of ? v q and ? v esr which peaks at the end of the on-cycle. calculate the required input capacitance and esr for a specified ripple using the following equa- tions: i load(max) is the maximum output current, ? i p-p is the peak-to-peak inductor current, and v pvin_ is the input supply voltage, v out_ is the regulator output voltage, and f sw is the switching frequency. esr v [mv] i i 2 [a] c i [a] v [v] v [v] v [v] f [mhz] i [a] v v [v] v [v] v [v] f [mhz] l esr load(max) pp pvin_ load(max) out_ pvin_ qsw pp pvin_ out_ out_ pvin_ sw [] [] [] m f h ? ? ? ? ? = + ? ? ? ? ? ? = ? ? ? ? ? ? = ? () ? ? lh ia pp [] [] = ? ? v [v] (v [v] v [v]) v [v] f [mhz] out_ pvin_ out_ pvin_ sw ? v [v] v [v] 1 (t [ s] f [mhz]) pvin_min out_ off(min) sw ? v [v] v [v] t [ s] f [mhz] pvin_max out_ on(min) sw
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers 16 ______________________________________________________________________________________ use the following equation to calculate the input ripple when only one regulator is enabled: the max15022 includes uvlo hysteresis to avoid possi- ble unintentional chattering during turn-on. use additional bulk capacitance if the input source impedance is high. if using a lower input voltage, additional input capacitance helps to avoid possible undershoot below the undervolt- age lockout threshold during transient loading. output-capacitor selection the allowed output-voltage ripple and the maximum deviation of the output voltage during load steps deter- mine the required output capacitance and its esr. the output ripple is mainly composed of ? v q (caused by the capacitor discharge) and ? v esr (caused by the voltage drop across the equivalent series resistance of the output capacitor). the equations for calculating the output capacitance and its esr are: where ? i p-p is the peak-to-peak inductor current, and f sw is the switching frequency. ? v esr and ? v q are not directly additive since they are out of phase from each other. if using ceramic capaci- tors, which generally have low esr, ? v q dominates. if using electrolytic capacitors, ? v esr dominates. the allowable deviation of the output voltage during fast load transients also affects the output capacitance, its esr, and its equivalent series inductance (esl). the output capacitor supplies the load current during a load step until the controller responds with an increased duty cycle. the response time (t response ) depends on the gain bandwidth of the controller (see the compensation-design guidelines section). the resistive drop across the output capacitors esr ( ? v esr ), the drop across the capacitors esl ( ? v esl ), and the capacitor discharge ( ? v q ) causes a voltage droop during the load-step (i step ). use a combination of low-esr tantalum/aluminum electrolyte and ceramic capacitors for better load transient and voltage ripple performance. non-leaded capacitors and capacitors in parallel help reduce the esl. keep the maximum out- put-voltage deviation below the tolerable limits of the electronics being powered. use the following equations to calculate the required output capacitance, esr, and esl for minimal output deviation during a load step: where i step is the load step, t step is the rise time of the load step, and t response is the response time of the controller. compensation design guidelines the max15022 uses a fixed-frequency, voltage-mode control scheme that regulates the output voltage by comparing the output voltage against a fixed reference. the subsequent error voltage that appears at the error-amplifier output (comp_) is compared against an internal ramp voltage to generate the required duty cycle of the pwm. a second order lowpass lc filter removes the switching harmonics and passes the dc component of the pwm signal to the output. the lc fil- ter has an attenuation slope of -40db/decade and intro- duces 180 of phase shift at frequencies above the lc resonant frequency. this phase shift in addition to the inherent 180 of phase shift of the regulators negative feedback system turns the feedback into unstable posi- tive feedback. the error amplifier and its associated circuitry must be designed to achieve a stable closed- loop system. the basic controller loop consists of a power modulator (comprised of the regulators pwm, associated circuitry, and lc filter), an output feedback divider, and an error amplifier. the power modulator has a dc gain set by v avin /v ramp where the ramp voltage (v ramp ) is a func- tion of the v avin and results in a fixed dc gain of 4v/v, providing effective feed-forward compensation of input- voltage supply dc variations. the feed-forward com- pensation eliminates the dependency of the power mod- ulators gain on the input voltage such that the feedback compensation of the error amplifier requires no modifi- cations for nominal input-voltage changes. the output filter is effectively modeled as a double-pole and a sin- gle zero set by the output inductance (l), the dc resis- tance of the inductor (dcr), the output capacitance (c out ), and its equivalent series resistance (esr). esr m v [mv] i [a] c i [a] t v [v] esl v [mv] t i [a] esr step out step response q esl step step [] [] [] [] [] ? ? ? ? = = = f s nh s cf i [a] 8 v [v] f [mhz] esr m 2 v [mv] i [a] out pp qsw esr pp [] [] = = ? ? ? ? ? ? ? i [a] i [a] v [v] v v [v] v [v] cin(rms) load(max) out_ pvin_ out_ pvin_ = ? ()
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers ______________________________________________________________________________________ 17 below are equations that define the power modulator: r out is the load resistance of the regulator, f lc is the resonant break frequency of the filter, and f esr is the esr zero of the output capacitor. see the closed-loop response and compensation of voltage-mode regulators for more information on f lc and f esr . the switching frequency (f sw ) is programmable between 500khz and 4mhz. typically, the crossover frequency (f co )the frequency at which the systems closed-loop gain is equal to unity (crosses 0db) should be set at or below one-tenth the switching fre- quency (f sw /10) for stable closed-loop response. the max15022 provides an internal voltage-mode error amplifier with its inverting input and its output available to the user for external frequency compensation. the flexi- bility of external compensation for each controller offers a wide selection of output filtering components, especial- ly the output capacitor. for cost-sensitive applications, use aluminum electrolytic capacitors while for space- sensitive applications, use low-esr tantalum or multilay- er ceramic chip (mlcc) capacitors at the output. the higher switching frequencies of the max15022 allow the use of mlcc as the primary filter capacitor(s). first, select the passive and active power components that meet the application output ripple, component size, and component cost requirements. second, choose the small-signal compensation components to achieve the desired closed-loop frequency response and phase margin as outlined below. closed-loop response and compensation of voltage-mode regulators the power modulators lc lowpass filter exhibits a vari- ety of responses, dependent on the value of the l and c and their parasitics. higher resistive parasitics reduce the q of the circuit, reducing the peak gain and phase of the system; however, efficiency is also reduced under these circumstances. one such response is shown in figure 4a. in this exam- ple, the esr zero occurs relatively close to the filters resonant break frequency, f lc . as a result, the power modulators uncompensated crossover is approximate- ly one third the desired crossover frequency, f co . note also, the uncompensated rolloff through the 0db plane follows a single-pole, -20db/decade slope and 90 of phase lag. in this instance, the inherent phase margin ensures a stable system; however, the gain-bandwidth product is not optimized. gain v v v v 4 4v/v f 1 2lc r esr r dcr 1 2lc f 1 2 esr c mod(dc) avin ramp avin avin lc out out out out esr out === = + + ? ? ? ? ? ? = max15022 fig04a magnitude (db) phase (degrees) -60 -40 -20 0 20 40 -80 100 1k 10k frequency (hz) 100k 1m 10m 10 -135 -90 -45 0 45 90 -180 |g mod | f lc f esr < g mod |g mod | asymptote figure 4a. power modulator gain and phase response with lossy bulk output capacitor(s) (aluminum) max15022 fig04b magnitude (db) phase (degrees) frequenc (hz) -60 -40 -20 0 20 40 60 80 -80 -135 -90 -45 0 45 90 135 180 -180 100 1k 10k 100k 1m 10m 10 < g ea g ea g mod f lc f esr f co < g mod figure 4b. power modulator and type ii compensator gain and phase response with lossy bulk output capacitor(s) (aluminum)
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers 18 ______________________________________________________________________________________ as seen in figure 4b, a type ii compensator provides for stable closed-loop operation, leveraging the +20db/ decade slope of the capacitors esr zero, while extend- ing the closed-loop gain bandwidth of the regulator. the zero crossover now occurs at approximately three times the uncompensated crossover frequency, f co . the type ii compensators midfrequency gain (approxi- mately 12db shown here) is designed to compensate for the power modulators attenuation at the desired crossover frequency, f co (gain e/a + gain mod = 0db at f co ). in this example, the power modulators inherent -20db/decade rolloff above the esr zero (f zero, esr ) is leveraged to extend the active regulation gain band- width of the voltage regulator. as shown in figure 4b, the net result is a three times increase in the regulators gain bandwidth while providing greater than 75 of phase margin (the difference between gain e/a and gain mod respective phases at crossover, f co ). other filter schemes pose their own problems. for instance, when choosing high-quality filter capacitor(s), e.g. mlccs, the inherent esr zero may occur at a much higher frequency, as shown in figure 4c. as with the previous example, the actual gain and phase response is overlaid on the power modulators asymptotic gain response. one readily observes the more dramatic gain and phase transition at or near the power modulators resonant frequency, f lc , versus the gentler response of the previous example. this is due to the filter components lower parasitic (dcr and esr) and corresponding higher frequency of the inherent esr zero. in this example, the desired crossover fre- quency occurs below the esr zero frequency. in this example, a compensator with an inherent midfre- quency double-zero response is required to mitigate the effects of the filters double-pole phase lag. this is available with the type iii topology. as demonstrated in figure 4d, the type iiis midfre- quency double-zero gain (exhibiting a +20db/decade slope, noting the compensators pole at the origin) is designed to compensate for the power modulators double-pole -40db/decade attenuation at the desired crossover frequency, f co (again, gain e/a + gain mod = 0db at f co ) (see figure 4d). in the above example, the power modulators inherent (midfrequency) -40db/decade rolloff is mitigated by the midfrequency double zeros +20db/decade gain to extend the active regulation gain bandwidth of the volt- age regulator. as shown in figure 4d, the net result is an approximate doubling in the controllers gain band- width while providing greater than 55 of phase margin (the difference between gain e/a and gain mod respec- tive phases at crossover, f co ). design procedures for both type ii and type iii com- pensators are shown below. magnitude (db) phase (degrees) frequency (hz) -60 -40 -20 0 20 40 -80 -135 -90 -45 0 45 90 -180 max15022 fig04c 100 1k 10k 100k 1m 10m 10 |g mod | |g mod | asymptote f lc f esr < g mod figure 4c. power modulator gain and phase response with low-parasitic capacitor(s) (mlccs) max15022 fig04d magnitude (db) phase (degrees) frequenc (hz) -60 -40 -20 0 20 40 60 80 -80 -203 -135 -68 0 68 135 203 270 -270 100 1k 10k 100k 1m 10m 10 < g ea g ea g mod f lc f esr f co < g mod figure 4d. power modulator and type iii compensator gain and phase response with low parasitic capacitors (mlccs)
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers ______________________________________________________________________________________ 19 type ii: compensation when f co > f zero, esr when the f co is greater than f esr , a type ii compensa- tion network provides the necessary closed-loop com- pensated response. the type ii compensation network provides a midband compensating zero and a high-fre- quency pole (see figures 5a and 5b). r f c f provides the midband zero f mid,zero , and r f c cf provides the high-frequency pole, f high,pole . use the following procedure to calculate the compen- sation network components. calculate the f esr and lc double pole, f lc : where c out is the regulator output capacitor and esr is the series resistance of c out . see the output- capacitor selection section for more information on cal- culating c out and esr. set the compensators leading zero, f z1 , at or below the filters resonant double-pole frequency from: set the compensators high-frequency pole, f p1 , at or below one-half the switching frequency, f sw : to maximize the compensators phase lead, set the desired crossover frequency, f co , equal to the geomet- ric mean of the compensators leading zero, f z1 , and high-frequency pole, f p1 , as follows: select the feedback resistor, r f , in the range of 3.3k ? to 30k ? . calculate the gain of the modulator (gain mod )com- prised of the regulators pwm, lc filter, feedback divider, and associated circuitryat the desired crossover fre- quency, f co , using the following equation: where v fb is the 0.6v (typ) fb_ input-voltage set-point, l is the value of the regulator inductor, esr is the series resistance of the output capacitor, and v out_ is the desired output voltage. the gain of the error amplifier (gain e/a ) in the midband frequencies is: the total loop gain is the product of the modulator gain and the error amplifier gain at f co and should be set equal to 1 as follows: gain mod x gain e/a = 1 so: 20 log 20 log 0db r r 4 esr x v 2 f l x v 1 10 r r 10 4 esr x v 2 f l x v f 1 fb co out_ f 1 fb co out_ + = = ? ? ? ? ? ? ? ? ? ? ? ? ? ? gain r [k ] r [k ] e/a f 1 = ? ? gain 4(v/v) esr [m ] 2 f [khz] l[ h] v [v] v [v] mod co fb out_ = () ? fff co z1 p1 = f f 2 p1 sw ff z1 lc f 1 2 esr c f 1 2lc esr out lc out = r 1 v ref r f fb_ comp_ v out_ r 2 c f c cf figure 5a. type ii compensation network gain (db) 1st asmptote ( r 1 c f ) -1 2nd asymptote r f r i 3rd asymptote ( r f c cf ) -1 (rad/sec) 1st pole (at origin) 2nd pole (r f c cf ) -1 1st zero (r f c f ) -1 ( ) -1 figure 5b. type ii compensation network response
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers 20 ______________________________________________________________________________________ solving for r 1 : where v fb is the 0.6v (typ) fb_ input-voltage set-point, l is the value of the regulator inductor, esr is the series resistance of the output capacitor, and v out_ is the desired output voltage. 1) c f is determined from the compensators leading zero, f z1 , and r f as follows: 2) c cf is determined from the compensators high-fre- quency pole, f p1 , and r f as follows: 3) calculate r 2 using the following equation: where v fb = 0.6v (typ) and v out_ is the output voltage of the regulator. type iii: compensation when f co < f esr as indicated above, the position of the output capaci- tors inherent esr zero is critical in designing an appro- priate compensation network. when low-esr ceramic output capacitors (mlccs) are used, the esr zero fre- quency (f esr ) is usually much higher than the desired crossover frequency (f co ). in this case, a type iii com- pensation network is recommended (see figure 6a). as shown in figure 6b, the type iii compensation net- work introduces two zeros and three poles into the con- trol loop. the error amplifier has a low-frequency pole at the origin, two zeros, and two higher frequency poles at the following frequencies: two midband zeros (f z1 and f z2 ) are designed to com- pensate for the pair of complex poles introduced by the lc filter. f p1 introduces a pole at zero frequency (integrator) for nulling dc output-voltage errors. f p1 = at the origin (0hz) depending on the location of the esr zero (f esr ), f p2 can be used to cancel it, or to provide additional atten- uation of the high-frequency output ripple. f p3 attenuates the high-frequency output ripple. since c cf << c f then: f 1 2 r c p3 fcf = f 1 2r cc 1 2r cc cc p3 ffcf f fcf fcf = () = + f 1 2rc p2 ii = f 1 2rc f 1 2c(rr) z1 ff z2 i1i = = + r[k] r[k] v [v] v [v] v [v] 21 fb out_ fb ?? = ? cf] 1 2 r [k ] f [khz] cf fp1 [ = ? c[f] 1 2 r [k ] f [khz] f fz1 = ? r [k ] r [k ] 4 esr[m ] v [v] 2 f [khz] l[ h] v [v] 1 ffb co out_ ? ?? = r 1 v ref r f fb_ comp_ v out_ r 2 c f c cf r i c i figure 6a. type iii compensation network gain (db) 1st asmptote ( r i c f ) -1 3rd asymptote ( r f c i ) -1 5th asymptote (r i c cf ) -1 (rad/sec) 1st pole (at origin) 2nd pole (r i c i ) -1 2nd zero (r 1 c i ) -1 3rd pole (r f c cf ) -1 1st zero (r f c f ) -1 4th asymptote r f r i ( ) 2nd asymptote r f r 1 ( ) -1 figure 6b. type iii compensation network response
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers ______________________________________________________________________________________ 21 the locations of the zeros and poles should be such that the phase margin peaks around f co . set the ratios of f co -to-f z and f p -to-f co equal to one anoth- er, e.g., f co = f p = 5 is a good number to get approximately f z f co 60 of phase margin at f co . whichever technique, it is important to place the two zeros at or below the double pole to avoid the conditional stability issue. the following procedure is recommended: 1) select a crossover frequency, f co , at or below one- tenth the switching frequency (f sw ): 2) calculate the lc double-pole frequency, f lc : where c out is the output capacitor of the regulator. 3) select the feedback resistor, r f , in the range of 3.3k ? to 30k ? . 4) place the compensators first zero at or below the output filters dou- ble-pole, f lc , as follows: 5) the gain of the modulator (gain mod )comprised of the regulators pwm, lc filter, feedback divider, and associated circuitryat the crossover frequency is: the gain of the error amplifier (gain e/a ) in midband fre- quencies is: the total loop gain is the product of the modulator gain and the error amplifier gain at f co should be equal to 1, as follows: gain mod x gain e/a = 1 so: solving for c i : 6) for those situations where f lc < f co < f esr < f sw /2, as with low-esr tantalum capacitors, the compen- sators second pole (f p2 ) should be used to cancel f esr . this provides additional phase margin. on the system bode plot, the loop gain maintains its +20db/decade slope up to 1/2 of the switching fre- quency verses flattening out soon after the 0db crossover. then set: f p2 = f esr if a ceramic capacitor is used, then the capacitor esr zero, f esr , is likely to be located even above 1/2 of the switching frequency, that is f lc < f co < f sw /2 < f esr . in this case, the frequency of the second pole (f p2 ) should be placed high enough not to significantly erode the phase margin at the crossover frequency. for example, f p2 can be set at 5 x f co , so that its contribution to phase loss at the crossover frequency f co is only about 11: f p2 = 5 x f co once f p2 is known, calculate r i : 7) place the second zero (f z2 ) at 0.2 x f co or at f lc , whichever is lower, and calculate r 1 using the fol- lowing equation: 8) place the third pole (f p3 ) at 1/2 the switching fre- quency and calculate c cf from: 9) calculate r 2 as: where v fb = 0.6v (typ). r[k] r[k] v [v] v [v] v [v] 21 fb out_ fb ?? = ? c[f] 1 2 0.5 f [mhz] r [k ] cf sw f n = () ? r[k ] 1 2 f [khz] c [ f] 1 z2 i ?= r[k ] 1 2 f [khz] c [ f] i p2 i ?= c pf] 2 f [khz] l[ h] c [ f] 4 r [k ] i co out f [ = () ? ? 4 1 (2 f [khz]) c [ f] l[ h] 2 f [khz] c [ f] r [k ] 1 co 2 out co i f = ? p ? gain 2 f [khz] c [ f] r [k ] e/a co i f = ? gain 4 1 (2 f [mhz]) l[ h] c [ f] mod co 2 out = ? c[f] 1 2 r [k ] 0.5 f [khz] f flc = ? f [mhz] 1 2 l[ h] c f] lc out [ f [khz] f [khz] 10 co sw f 1 2rc z1 ff =
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers 22 ______________________________________________________________________________________ ldo controllers design procedure pnp pass transistors selection the pass transistors must meet specifications for current gain (?), input capacitance, collector-emitter saturation voltage, and power dissipation. the transistors current gain limits the guaranteed maximum output current to: where i b3/4(min) is the minimum base-drive current and r pull is the pullup resistor connected between the transistors base and emitter. in addition, to avoid premature dropout, v ce-sat must be less than or equal to (v pvin_(min) - v out3/4 ). furthermore, the transistors current gain increases the linear regulators dc loop gain (see the stability requirements section), so excessive gain destabilizes the output. therefore, transistors with high current gain at the maximum output current, such as darlington transistors, are not recommended. the transistors input capacitance and input resistance also create a second pole, which could be low enough to destabilize the ldo when the output is heavily loaded. the transistors saturation voltage at the maximum out- put current determines the minimum input-to-output volt- age differential that the linear regulator supports. alternately, the packages power dissipation could limit the useable maximum input-to-output voltage differential. the maximum power-dissipation capability of the tran- sistors package and mounting must support the actual power dissipation in the device without exceeding the maximum junction temperature. the power dissipated equals the maximum load current multiplied by the maximum input-to-output voltage differential. output 3 and output 4 voltage selection the max15022 positive linear-regulator output voltage is set with a resistive divider from the desired output (v out3/4 ) to fb3/4 to sgnd (see figures 7 and 8). first, select the r 2fb3/4 resistance value (below 30k ? ). then, solve for r 1fb3/4 : where v out3/4 can support output voltages as low as 0.6v and v fb3/4 is 0.6v (typ). stability requirements the max15022s b3 and b4 outputs are designed to drive bipolar pnp transistors. these pnp transistors form linear regulators with positive outputs. an internal transconductance amplifier drives the external pass transistors. the transconductance amplifier, pass tran- sistors specifications, the base-emitter resistor, and the output capacitor determine the loop stability. the total dc loop gain (a v ) is the product of the gains of the internal transconductance amplifier, the gain from base to collector of the pass transistor, and the attenua- tion of the feedback divider. the transconductance ampli- fier regulates the output voltage by controlling the pass transistors base current. its dc gain is approximately: where g c_ is the transconductance of the internal amplifier and is typically 1.2ma/mv, r p1/2 is the resistor across the base and the emitter of the pass transistor in k ? , and r in is the input resistance of the pass transis- tor, and can be calculated by: the dc gain for the pass transistor (a p ), including the feedback divider, is approximately: the total dc loop gain for output 3 and output 4 is: the output capacitance (c out_ ) and the load resis- tance (r out_ ) create a dominant pole (f pole1 ) at: f [khz] 2c r i [ma] 2 c v [v] pole1 out3/4 out3/4 out3/4(max) out3/4 out3/4 = = 1 [] [] [] fk f ? ag rr rr a vc_ in p1/2 in p1/2 p = + ? ? ? ? ? ? where g ima 26 mv mpnp out3/4 ? = [] [] . ag r(rr) r pmpnp out3/4 1fb3/4 2fb3/4 out3/4 = + + ? r rr r rr 1fb3/4 2fb3/4 2fb3/4 1fb3/4 2f + ? ? ? ? ? ? + b b3/4 r 26[mv] i in out3/4 [] [] kx a ?= ? ? ? ? ? ? g rr rr c_ in p1/2 in p1/2 + ? ? ? ? ? ? rr v [v] v [v] 1 1fb3/4 2fb3/4 out3/4 fb3/4 [] [] kk ?? = ? ? ? ? ? ? ? i [a] i [a] v [v] r out3/4 b3/4(min) be pull = ? ? ? ? ? ? ? [] ?
the input capacitance to the base of the pass transistor (c qin ), any external base-to-emitter capacitance (c be , see the base-drive noise reduction section), the tran- sistors input resistance (r in ), and the base-to-emitter pullup resistor (r p_ ) set a second pole: to maintain the stability, at a minimum the following condition must be satisfied: i.e., the second pole must occur above the unity-gain crossover. at heavy output load, we can simplify as fol- lows: and hence, the output capacitance (c out3/4 ) must sat- isfy the following equation: where: ? is the current gain of the pnp transistor, g c_ is the transconductance of the internal amplifier (1.2ma/mv typical), and f is the forward transit time of the pnp transistor. for example, using a pnp transistor with a ? of 120, f of 400ps, g c_ = 1.2ma/mv, and = 0.5 for a 1.2v output voltage, c out must be at least 3.9f. if the second pole occurs well after unity-gain crossover, the linear regulator remains stable. if not, then increase the output capacitance, c out3/4 , such that: if the output capacitor is a high-esr capacitor, then cancel the esr zero with a pole at fb3/4. this is accomplished by adding a capacitor (c fb3/4 ) from fb3/4 to ground, such that: for a sufficiently low output capacitance, choose a fast pnp transistor without an excessively high ?. note, selecting a transistor with a ? that is too low can adversely impact load regulation. output 3 and output 4 capacitors connect c out (as determined above) between the lin- ear regulators output and ground, as close as possible to the max15022 and the external pass transistors. depending on the selected pass transistor, larger capacitor values may be required for stability (see the stability requirement section). once the minimum capacitor value for stability is deter- mined, verify that the linear regulators output does not contain excessive noise. although adequate for stabili- ty, small capacitor values can provide too much band- width, making the linear regulator sensitive to noise. larger capacitor values reduce the bandwidth, thereby reducing the regulators noise sensitivity. base-drive noise reduction the high-impedance base driver is susceptible to sys- tem noise, especially when the linear regulator is lightly loaded. capacitively coupled switching noise or induc- tively coupled emi on the base drive may cause fluctu- ations in the base current, which appear as noise on the linear regulators output. to avoid this, keep the base-driver traces away from the step-down converter and as short as possible to minimize noise coupling. a bypass capacitor (c be ) can be placed across the base-to-emitter resistor. this bypass capacitor, in addi- tion to the transistors input capacitance, reduces the frequency of the second pole (f pole2 ) that could desta- bilize the linear regulator. therefore, the stability requirements determine the maximum base-to-emitter capacitance (c be ) that can be added. a capacitance in the range of 470pf to 2200pf is recommended. c 2 (r r ) f [khz] fb3/4 1fb3/4 2fb3/4 esr [] [] f k = 1 ? f2f pole2 cout_ > = + r rr 2fb3/4 1fb3/4 2fb3/4 cg out3/4 c_ 2 > ? f rrr ccg rr g out3/4 1fb3/4 2fb3/4 be qin m pnp f p1/2 in m pnp << + << >> ? ? af f v pole1 pole2 < where r r r . total in p1/2 = f [khz] 2c c r pole2 be qin total = + () 1 [] [] fk ? max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers ______________________________________________________________________________________ 23
max15022 minimum load requirements (linear regulators) under no-load conditions, leakage currents from the pass transistors supply the output capacitor, even when the transistor is off. generally, this is not a prob- lem since the feedback resistors current drains the excess charge. however, charge can build up on the output capacitor over temperature, making output volt- age rise above its set point. care must be taken to ensure the feedback resistors current exceeds the pass transistors leakage current over the entire tem- perature range. thermal consideration the power dissipated by the pass transistor is calculat- ed by: where v in is the input to the transistor of the ldo. heatsink the transistor adequately to prevent a thermal runaway condition. refer to the transistor data sheet for thermal calculations. applications information pcb layout guidelines careful pcb layout is critical to achieve clean and sta- ble operation. follow these guidelines for good pcb layout: 1) place decoupling capacitors as close as possible to the ic pins. 2) keep sgnd and pgnd isolated. connect them at one single point typically close to the negative ter- minal of the input filter capacitor. use as short a trace as possible. 3) route high-speed switching nodes (lx_) away from sensitive analog areas (fb_, comp_, b_, and en_). 4) distribute the power components evenly across the board for proper heat dissipation. 5) ensure all feedback connections are short and direct. place feedback resistors as close as possi- ble to the ic. 6) place the output capacitors close to the load. 7) connect the max15022 exposed pad to a large copper plane to maximize its power dissipation capability. thermal resistances can be obtained using the method described in jedec specification jesd51-7. connect the exposed pad to sgnd plane. do not connect the exposed pad to the sgnd pin directly underneath the ic. 8) use 2oz. copper to keep trace inductance and resistance to a minimum. thin copper pcbs can compromise efficiency since high currents are involved in the application. also thicker copper con- ducts heat more effectively, thereby reducing ther- mal impedance. 9) a reference pcb layout included in the max15022 evaluation kit is also provided to further aid layout. pvv i p3/4 in out3/4 out3/4 = () ? dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers 24 ______________________________________________________________________________________
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers ______________________________________________________________________________________ 25 typical operating circuits c i2 max15022 lx2 pgnd2 en1 dvdd1 rt sel comp1 sgnd avin en2 pvin2 dvdd2 c dd1 c cf2 c f2 r f2 r t r i2 r 1 r 2en4 r 1en4 r p2 r 1en3 r 1fb3 r 2fb3 r p1 c 1 v in r 1fb1 r i1 r s2 l 2 r 2fb2 r 2fb1 r 1fb2 c t c 2 c out3 c p1 c i1 c out2 v out2 v avin v out1 c s2 c in2 c dd2 fb2 v in pvin1 c in1 v in comp2 c cf1 c f1 r f1 lx1 pgnd1 fb1 pgnd sgnd r s1 l 1 c out1 v out1 v avin c s1 r 1en2 r 2en2 b3 fb4 en4 en3 fb3 b4 q 1 q 2 v out2 v out3 v out4 r 2en3 r 2fb4 r 1fb4 c out4 c e1 c p2 c e2 figure 7. max15022 double buck with tracking and two additional ldos
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers 26 ______________________________________________________________________________________ typical operating circuits (continued) c i2 max15022 lx2 pgnd2 en1 dvdd1 rt sel comp1 sgnd avin en2 pvin2 dvdd2 c dd1 c cf2 c f2 r f2 r t r i2 r 1 c 1 v in r 1fb1 r i1 r s2 l 2 r 2fb2 r 2fb1 r 1fb2 c t c 2 c i1 c out2 v out2 v avin c s2 c in2 c dd2 fb2 v in pvin1 c in1 v in comp2 c cf1 c f1 r f1 lx1 pgnd1 fb1 r s1 l 1 c out1 v out1 c s1 r 2en4 r 1en4 r p2 r 1en3 r 1fb3 r 2fb3 r p1 c out3 c p1 pgnd sgnd b3 fb4 en4 en3 fb3 b4 q 1 q 2 v out3 v out4 r 2en3 r 2fb4 r 1fb4 c out4 c e1 c p2 c e2 figure 8. max15022 double buck with sequencing and two additional ldos
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers ______________________________________________________________________________________ 27 chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 28 tqfn-ep t2855+6 21-01 40 90-0026
max15022 dual, 4a/2a, 4mhz, step-down dc-dc regulator with dual ldo controllers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 5/08 initial release 1 7/11 added the MAX15022ATI/v+ to the data sheet; added package thermal characteristics to absolute maximum ratings . 1, 2

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